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ltc1863/ltc1867 1 18637f applicatio s u block diagra w features descriptio u n industrial process control n high speed data acquisition n battery operated systems n multiplexed data acquisition systems n imaging systems n sample rate: 200ksps n 16-bit no missing codes and 2lsb max inl n 8-channel multiplexer with: single ended or differential inputs and unipolar or bipolar conversion modes n spi/microwire tm serial i/o n signal-to-noise ratio: 89db n single 5v operation n on-chip or external reference n low power: 1.3ma at 200ksps, 0.76ma at 100ksps n sleep mode n automatic nap mode between conversions n 16-pin narrow ssop package 12-/16-bit, 8-channel 200ksps adcs the ltc ? 1863/ltc1867 are pin-compatible, 8-channel 12-/16-bit a/d converters with serial i/o, and an internal reference. the adcs typically draw only 1.3ma from a single 5v supply. the 8-channel input multiplexer can be configured for either single-ended or differential inputs and unipolar or bipolar conversions (or combinations thereof). the automatic nap and sleep modes benefit power sensitive applications. the ltc1867s dc performance is outstanding with a 2lsb inl specification and no missing codes over tem- perature. the signal-to-noise ratio (snr) for the ltc1867 is typically 89db, with the internal reference. housed in a compact, narrow 16-pin ssop package, the ltc1863/ltc1867 can be used in space-sensitive as well as low-power applications. , ltc and lt are registered trademarks of linear technology corporation. ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 v dd gnd sdi sdo sck cs/conv v ref 18637 bd 12-/16-bit 200ksps adc + serial port analog input mux refcomp 9 internal 2.5v ref ltc1863/ltc1867 microwire is a trademark of national semiconductor corp. output code 0 inl (lbs) 49152 18637 go1 16384 32768 65536 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 integral nonlinearity vs output code (ltc1867)
ltc1863/ltc1867 2 18637f top view gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com v dd gnd sdi sdo sck cs/conv v ref refcomp co verter characteristics u supply voltage (v dd ) ................................... C0.3v to 6v analog input voltage ch0-ch7/com (note 3) .......... C 0.3v to (v dd + 0.3v) v ref , refcomp (note 4)......... C 0.3v to (v dd + 0.3v) digital input voltage (sdi, sck, cs/conv) (note 4) .................................................C 0.3v to 10v digital output voltage (sdo) ....... C 0.3v to (v dd + 0.3v) power dissipation .............................................. 500mw operating temperature range ltc1863c/ltc1867c/ltc1867ac .......... 0 c to 70 c ltc1863i/ltc1867i/ltc1867ai ........ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 110 c, q ja = 95 c/w ltc1863cgn ltc1863ign ltc1867cgn ltc1867ign ltc1867acgn ltc1867aign absolute axi u rati gs w ww u package/order i for atio uu w (notes 1, 2) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with external reference (notes 5, 6) ltc1863 ltc1867 ltc1867a parameter conditions min typ max min typ max min typ max units resolution l 12 16 16 bits no missing codes l 12 15 16 bits integral linearity error unipolar (note 7) l 1 4 2 lsb bipolar l 1 4 2.5 lsb differential linearity error l 1 C2 3 C1 1.75 lsb transition noise 0.1 0.74 0.74 lsb rms offset error unipolar (note 8) l 3 32 32 lsb bipolar l 4 64 64 lsb offset error match unipolar 1 2 2 lsb bipolar 1 2 2 lsb offset error drift 0.5 0.5 0.5 ppm/ c gain error unipolar 6 96 64 lsb bipolar 6 96 64 lsb gain error match 1 4 2 lsb gain error tempco internal reference 15 15 15 ppm/ c external reference 2.7 2.7 2.7 ppm/ c power supply sensitivity v dd = 4.75v C 5.25v 1 5 5 lsb consult ltc marketing for parts specified with wider operating temperature ranges. gn part marking 1863 1867 (note 5) dy a ic accuracy u w ltc1863 ltc1867/ltc1867a symbol parameter conditions min typ max min typ max units snr signal-to-noise ratio 1khz input signal 73.6 89 db s/(n+d) signal-to-(noise + distortion) ratio 1khz input signal 73.5 88 db
ltc1863/ltc1867 3 18637f dy a ic accuracy u w a alog i put u u i ter al refere ce characteristics uu u digital i puts a d digital outputs u u ltc1863 ltc1867/ltc1867a symbol parameter conditions min typ max min typ max units thd total harmonic distortion 1khz input signal, up to 5th harmonic C94.5 C 95 db peak harmonic or spurious noise 1khz input signal C94.5 C 95 db channel-to-channel isolation 100khz input signal C100 C117 db full power bandwidth C3db point 1.25 1.25 mhz (note 5) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) (note 5) symbol parameter conditions min typ max units analog input range unipolar mode (note 9) l 0-4.096 v bipolar mode l 2.048 v c in analog input capacitance for ch0 to between conversions (sample mode) 32 pf ch7/com during conversions (hold mode) 4 pf t acq sample-and-hold acquisition time l 1.5 1.1 m s input leakage current on channels, chx = 0v or v dd l 1 m a parameter conditions min typ max units v ref output voltage i out = 0 2.480 2.500 2.520 v v ref output tempco i out = 0 15 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.43 mv/v v ref output resistance ? i out ? 0.1ma 6 k w refcomp output voltage i out = 0 4.096 v symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 2pf v oh high level output voltage (sdo) v dd = 4.75v, i o = C10 m a 4.75 v v dd = 4.75v, i o = C200 m a l 4 4.74 v v ol low level output voltage (sdo) v dd = 4.75v, i o = 160 m a 0.05 v v dd = 4.75v, i o = 1.6ma l 0.10 0.4 v i source output source current sdo = 0v C32 ma i sink output sink current sdo = v dd 19 ma hi-z output leakage cs/conv = high, sdo = 0v or v dd l 10 m a hi-z output capacitance cs/conv = high (note 10) l 15 pf data format unipolar straight binary bipolar twos complement the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ltc1863/ltc1867/ltc1867a ltc1863/ltc1867/ltc1867a ltc1863/ltc1867/ltc1867a
ltc1863/ltc1867 4 18637f symbol parameter conditions min typ max units v dd supply voltage (note 9) 4.75 5.25 v i dd supply current f sample = 200ksps l 1.3 1.8 ma nap mode 150 m a sleep mode l 0.2 3 m a p diss power dissipation l 6.5 9 mw ti i g characteristics u w the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) symbol parameter conditions min typ max units f sample maximum sampling frequency l 200 khz t conv conversion time l 3 3.5 m s t acq acquisition time l 1.5 1.1 m s f sck sck frequency 40 mhz t 1 cs/conv high time short cs/conv pulse mode l 40 100 ns t 2 sdo valid after sck c l = 25pf (note 11) l 13 22 ns t 3 sdo valid hold time after sck c l = 25pf l 511 ns t 4 sdo valid after cs/conv c l = 25pf l 10 30 ns t 5 sdi setup time before sck - l 15 C6 ns t 6 sdi hold time after sck - l 10 4 ns t 7 sleep mode wake-up time c refcomp = 10 m f, c vref = 2.2 m f60ms t 8 bus relinquish time after cs/conv - c l = 25pf l 20 40 ns note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma without latchup. note 4: when these pin voltages are taken below gnd, they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f sample = 200ksps at 25 c, t r = t f = 5ns and v in C = 2.5v for bipolar mode unless otherwise specified. note 6: linearity, offset and gain error specifications apply for both unipolar and bipolar modes. the inl and dnl are tested in bipolar mode. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: unipolar offset is the offset voltage measured from +1/2lsb when the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001 for ltc1867 and between 0000 0000 0000 and 0000 0000 0001 for ltc1863. bipolar offset is the offset voltage measured from C1/2lsb when output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for ltc1867, and between 0000 0000 0000 and 1111 1111 1111 for ltc1863. note 9: recommended operating conditions. the input range of 2.048v for bipolar mode is measured with respect to v in C = 2.5v. note 10: guaranteed by design, not subject to test. note 11: t 2 of 25ns maximum allows f sck up to 20mhz for rising capture with 50% duty cycle and f sck up to 40mhz for falling capture (with 3ns setup time for the receiving logic). power require e ts w u the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ltc1863/ltc1867/ltc1867a ltc1863/ltc1867/ltc1867a
ltc1863/ltc1867 5 18637f frequency (khz) 0 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 75 18637 g04 25 50 100 amplitude (db) frequency (khz) 0 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 75 18637 g05 25 50 100 amplitude (db) active channel input frequency (khz) 1 resulting amplitude on selected channel (db) ?0 ?0 ?00 ?10 ?20 ?30 ?40 10 100 1000 18637 g06 input frequency (khz) 1 amplitude (db) 100 90 80 70 60 50 40 30 20 10 100 18637 g07 input frequency (khz) 1 amplitude (db) 100 90 80 70 60 50 40 30 20 10 100 18637 g08 input frequency (khz) 1 amplitude (db) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 10 100 18637 g09 adjacent pair nonadjacent pair snr = 88.8db sinad = 87.9db thd = 95db f sample = 200ksps internal reference snr = 90db sinad = 88.5db thd = 94db f sample = 200ksps v ref = 0v refcomp = ext 5v output code 0 inl (lsb) 49152 18637 go1 16384 32768 65536 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 output code 0 dnl (lsb) 49152 16384 32768 65536 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 18637 go2 code ? counts 4 18637 go3 ? ? 0 ? 3 2 1 2500 2000 1500 1000 500 0 1 26 276 2152 579 122 5 0 935 typical perfor a ce characteristics uw integral nonlinearity vs output code differential nonlinearity vs output code histogram for 4096 conversions 4096 points fft plot (f in = 1khz) 4096 points fft plot (f in = 1khz, refcomp = external 5v) crosstalk vs input frequency signal-to-noise ratio vs frequency signal-to-(noise + distortion) vs input frequency total harmonic distortion vs input frequency (ltc1867)
ltc1863/ltc1867 6 18637f f sample (ksps) 1 supply current (ma) 2.0 1.5 1.0 0.5 0 10 100 1000 18637 g10 supply voltage (v) 4.5 supply current (ma) 5.5 18637 g11 4.75 5.0 5.25 1.5 1.4 1.3 1.2 1.1 1.0 temperature ( c) ?0 supply current (ma) 1.5 1.4 1.3 1.2 1.1 1.0 ?5 02550 18637 g12 75 100 v dd = 5v v dd = 5v f sample = 200ksps v dd = 5v f sample = 200ksps output code 0 inl (lbs) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1024 2048 2560 18637 g13 512 1536 3072 3584 4096 output code 0 dnl (lbs) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1024 2048 2560 18637 g14 512 1536 3072 3584 4096 typical perfor a ce characteristics uw supply current vs f sample supply current vs supply voltage supply current vs temperature (ltc1863/ltc1867) differential nonlinearity vs output code (ltc1863) integral nonlinearity vs output code (ltc1863)
ltc1863/ltc1867 7 18637f uu u pi fu ctio s cho-ch7/com (pins 1-8): analog input pins. analog inputs must be free of noise with respect to gnd. ch7/ com can be either a separate channel or the common minus input for the other channels. refcomp (pin 9): reference buffer output pin. bypass to gnd with 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor (4.096v nominal). to overdrive refcomp, tie v ref to gnd. v ref (pin 10): 2.5v reference output. this pin can also be used as an external reference buffer input for improved accuracy and drift. bypass to gnd with 2.2 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor. cs/conv (pin 11): this input provides the dual function of initiating conversions on the adc and also frames the serial data transfer. sck (pin 12): shift clock. this clock synchronizes the serial data transfer. sdo (pin 13): digital data output. the a/d conversion result is shifted out of this output. straight binary format for unipolar mode and twos complement format for bipolar mode. sdi (pin 14): digital data input pin. the a/d configuration word is shifted into this input. gnd (pin 15): analog and digital gnd. v dd (pin 16): analog and digital power supply. bypass to gnd with 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor. test circuits uu u typical co ectio diagra u u ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com v dd gnd sdi sdo sck cs/conv v ref refcomp ltc1863/ ltc1867 + + digital i/o 5v 4.096v 10 f 2.2 f 2.5v 2.048v differential inputs 4.096v single-ended input 18637 tcd 3k (a) hi-z to v oh and v ol to v oh c l 3k 5v dn dn (b) hi-z to v ol and v oh to v ol c l 18637 tc01 3k (a) v oh to hi-z c l 3k 5v dn dn (b) v ol to hi-z c l 18637 tc02 load circuits for access timing load circuits for output float delay
ltc1863/ltc1867 8 18637f ti i g diagra s w u w t 5 (sdi setup time before sck - ), t 6 (sdi hold time after sck - ) 50% 50% t 3 0.4v t 7 (sleep mode wake-up time) t 7 sck cs/conv t 8 (bus relinquish time) t 8 cs/conv sdo 2.4v t 4 (sdo valid after conv ) t 4 cs/conv sdo 2.4v 0.4v 0.4v t 6 2.4v 0.4v t 5 sck sdi 2.4v 2.4v 0.4v 2.4v 0.4v sdo 1867 td sleep bit (slp = 0) read-in 10% 90% hi-z hi-z t 1 (for short pulse mode) t 2 (sdo valid before sck - ), t 3 (sdo valid hold time after sck ) t 1 cs/conv t 2 sck 50% 50% overview the ltc1863/ltc1867 are complete, low power multi- plexed adcs. they consist of a 12-/16-bit, 200ksps ca- pacitive successive approximation a/d converter, a preci- sion internal reference, a configurable 8-channel analog input multiplexer (mux) and a serial port for data transfer. conversions are started by a rising edge on the cs/conv input. once a conversion cycle has begun, it cannot be restarted. between conversions, the adcs receive an input word for channel selection and output the conversion result, and the analog input is acquired in preparation for the next conversion. in the acquire phase, a minimum time of 1.5 m s will provide enough time for the sample-and-hold capacitors to acquire the analog signal. during the conversion, the internal differential 16-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). the input is sucessively compared with the binary weighted charges supplied by the differential capacitive dac. bit decisions are made by a low-power, differential comparator. at the end of a conversion, the dac output balances the analog input. the sar contents (a 12-/16-bit data word) that represent the analog input are loaded into the 12-/16-bit output latches. applicatio s i for atio wu uu
ltc1863/ltc1867 9 18637f applicatio s i for atio wu uu examples of multiplexer options ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com gnd ( ) 8 single-ended + + + + + + + 4 differential + ( ) + ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com ( ) 7 single-ended to ch7/com + + + + + + + + ( ) + ( ) + ( ) ( + ) ( + ) ( + ) ( + ) gnd ( ) combinations of differential and single-ended + + + + + + { { { { { { 18637 ai01 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com analog input multiplexer the analog input multiplexer is controlled by a 7-bit input data word. the input data word is defined as follows: sd os s1 s0 com uni slp sd = single/differential bit os = odd/sign bit s1 = address select bit 1 s0 = address select bit 0 com = ch7/com configuration bit uni = unipolar/bipolar bit slp = sleep mode bit applicatio s i for atio wu uu tables 1 and 2 show the configurations when com = 0, and com = 1. table 1. channel configuration (when com = 0, ch7/com pin is used as ch7) channel configuration sd os s1 s0 com + - 00000 ch0 ch1 00010 ch2 ch3 00100 ch4 ch5 00110 ch6 ch7 01000 ch1 ch0 01010 ch3 ch2 01100 ch5 ch4 01110 ch7 ch6 10000 ch0 gnd 10010 ch2 gnd 10100 ch4 gnd 10110 ch6 gnd 11000 ch1 gnd 11010 ch3 gnd 11100 ch5 gnd 11110 ch7 gnd table 2. channel configuration (when com = 1, ch7/com pin is used as common) channel configuration sd os s1 s0 com "+" "-" 10001 ch0 ch7/com 10011 ch2 ch7/com 10101 ch4 ch7/com 10111 ch6 ch7/com 11001 ch1 ch7/com 11011 ch3 ch7/com 11101 ch5 ch7/com changing the mux assignment on the fly ch7/com (unused) ch7/com ( ) 1st conversion 2nd conversion + + + + + { { { { ch2 ch3 ch4 ch5 ch2 ch3 ch4 ch5 18637 ai02
ltc1863/ltc1867 10 18637f driving the analog inputs the analog inputs of the ltc1863/ltc1867 are easy to drive. each of the analog inputs can be used as a single- ended input relative to the gnd pin (ch0-gnd, ch1-gnd, etc) or in pairs (ch0 and ch1, ch2 and ch3, ch4 and ch5, ch6 and ch7) for differential inputs. in addition, ch7 can act as a com pin for both single-ended and differential modes if the com bit in the input word is high. regardless of the mux configuration, the + and C inputs are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charg- ing the sample-and-hold capacitors during the acquire mode. in conversion mode, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low then the ltc1863/ltc1867 inputs can be driven directly. more acquisition time should be allowed for a higher impedance source. the following list is a summary of the op amps that are suitable for driving the ltc1863/ltc1867. more detailed information is available in the linear technology data books or linear technology website. lt1007 - low noise precision amplifier. 2.7ma supply current 5v to 15v supplies. gain bandwidth product 8mhz. dc applications. lt1097 - low cost, low power precision amplifier. 300 m a supply current. 5v to 15v supplies. gain bandwidth product 0.7mhz. dc applications. lt1227 - 140mhz video current feedback amplifier. 10ma supply current. 5v to 15v supplies. low noise and low distortion. lt1360 - 37mhz voltage feedback amplifier. 3.8ma sup- ply current. 5v to 15v supplies. good ac/dc specs. lt1363 - 50mhz voltage feedback amplifier. 6.3ma sup- ply current. good ac/dc specs. lt1364/lt1365 - dual and quad 50mhz voltage feedback amplifiers. 6.3ma supply current per amplifier. good ac/dc specs. lt1468 - 90mhz, 22v/ m s 16-bit accurate amplifier lt1469 - dual lt1468 input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1863/ltc1867 noise and distortion. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for instance, figure 1 shows a 50 w source resistor and a 2000pf capacitor to ground on the input will limit the input bandwidth to 1.6mhz. the source impedance has to be kept low to avoid gain error and degradation in the ac performance. the capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sampling glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linear- ity. carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resis- tors are much less susceptible to both problems. applicatio s i for atio wu uu
ltc1863/ltc1867 11 18637f dc performance one way of measuring the transition noise associated with a high resolution adc is to use a technique where a dc signal is applied to the input of the adc and the resulting output codes are collected over a large number of conver- sions. for example, in figure 2 the distribution of output codes is shown for a dc input that had been digitized 4096 times. the distribution is gaussian and the rms code transition noise is about 0.74lsb. applicatio s i for atio wu uu 1867 f01a ch0 gnd ltc1863/ ltc1867 refcomp 2000pf 10 m f 50 analog input 1000pf 1867 f01b ch0 ch1 ltc1863/ ltc1867 refcomp 1000pf 1000pf 10 m f 50 50 differential analog inputs figure 1a. optional rc input filtering for single-ended input figure 1b. optional rc input filtering for differential inputs figure 2. ltc1867 histogram for 4096 conversions dynamic performance fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adcs spectral content can be examined for frequencies outside the fundamental. signal-to-noise ratio the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 3 shows a typical sinad of 87.9db with a 200khz sampling rate and a 1khz input. when an external 5v is applied to refcomp (tie v ref to gnd), a signal-to-noise ratio of 90db can be achieved. code ? counts 4 18637 go3 ? ? 0 ? 3 2 1 2500 2000 1500 1000 500 0 1 26 276 2152 579 122 5 0 935 figure 3. ltc1867 nonaveraged 4096 point fft plot frequency (khz) 0 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 75 18637 g04 25 50 100 amplitude (db) snr = 88.8db sinad = 87.9db thd = 95db f sample = 200ksps internal reference total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd vvv v v n = ++ + 20 2 2 3 2 4 22 1 log ...
ltc1863/ltc1867 12 18637f digital interface the ltc1863/ltc1867 have very simple digital interface that is enabled by the control input, cs/conv. a logic rising edge applied to the cs/conv input will initiate a conversion. after the conversion, taking cs/conv low will enable the serial port and the adc will present digital data in twos complement format in bipolar mode or straight binary format in unipolar mode, through the sck/sdo serial port. internal clock the internal clock is factory trimmed to achieve a typical conversion time of 3 m s and a maximum conversion time, 3.5 m s, over the full operating temperature range. the typical acquisition time is 1.1 m s, and a throughput sam- pling rate of 200ksps is tested and guaranteed. automatic nap mode the ltc1863/ltc1867 go into automatic nap mode when cs/conv is held high after the conversion is complete. with a typical operating current of 1.3ma and automatic 150 m a nap mode between conversions, the power dissi- pation drops with reduced sample rate. the adc only keeps the v ref and refcomp voltages active when the part is in the automatic nap mode. the slower the sample rate allows the power dissipation to be lower (see figure 5). r2 r3 reference amp 10 f 2.2 f refcomp gnd v ref r1 6k 10 9 15 2.5v 4.096v ltc1863/ltc1867 1867 f04a bandgap reference 10 0.1 m f 10 m f 1867 f04b lt1019a-2.5 v out v in 5v v ref ltc1863/ ltc1867 gnd refcomp 15 9 + 2.2 m f where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. internal reference the ltc1863/ltc1867 has an on-chip, temperature com- pensated, curvature corrected, bandgap reference that is factory trimmed to 2.5v. it is internally connected to a reference amplifier and is available at v ref (pin 10). a 6k resistor is in series with the output so that it can be easily overdriven by an external reference if better drift and/or accuracy are required as shown in figure 4. the reference amplifier gains the v ref voltage by 1.638v to 4.096v at refcomp (pin 9). this reference amplifier compensation pin, refcomp, must be bypassed with a 10 m f ceramic or tantalum in parallel with a 0.1 m f ceramic for best noise performance. figure 4b. using the lt1019-2.5 as an external reference figure 4a. lt1867 reference circuit applicatio s i for atio wu uu f sample (ksps) 1 supply current (ma) 2.0 1.5 1.0 0.5 0 10 100 1000 18637 g10 v dd = 5v figure 5. supply current vs f sample
ltc1863/ltc1867 13 18637f if the cs/conv returns low during a bit decision, it can create a small error. for best performance ensure that the cs/conv returns low either within 100ns after the conver- sion starts (i.e. before the first bit decision) or after the conversion ends. if cs/conv is low when the conversion ends, the msb bit will appear on sdo at the end of the conversion and the adc will remain powered up. sleep mode if the slp = 1 is selected in the input word, the adc will enter sleep mode and draw only leakage current (pro- vided that all the digital inputs stay at gnd or v dd ). after release from the sleep mode, the adc need 60ms to wake up (2.2 m f/10 m f bypass capacitors on v ref /refcomp pins). broad layout and bypassing to obtain the best performance, a printed circuit board with a ground plane is required. layout for the printed circuit board should ensure digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital signal alongside an analog signal. applicatio s i for atio wu uu all analog inputs should be screened by gnd. v ref , refcomp and v dd should be bypassed to this ground plane as close to the pin as possible; the low impedance of the common return for these bypass capacitors is essen- tial to the low noise operation of the adc. the width for these tracks should be as wide as possible. timing and control conversion start is controlled by the cs/conv digital input. the rising edge transition of the cs/conv will start a conversion. once initiated, it cannot be restarted until the conversion is complete. figures 6 and 7 show the timing diagrams for two types of cs/conv pulses. example 1 (figure 6) shows the ltc1863/ltc1867 oper- ating in automatic nap mode with cs/conv signal staying high after the conversion. automatic nap mode provides power reduction at reduced sample rate. the adcs can also operate with the cs/conv signal returning low before the conversion ends. in this mode (example 2, figure 7), the adcs remain powered up. figures 8 and 9 are the transfer characteristics for the bipolar and unipolar mode. s0 sd 0s s1 com uni slp d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1/f sck cs/conv sck sdi sdo (ltc1863) hi-z d12 d15 d14 d13 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hi-z 12345678910111213141516 1867 f06 don't care don't care not needed for ltc1863 t conv nap mode sdo (ltc1867) msb msb figure 6. example 1, cs/conv starts a conversion and remains high until next data transfer. with cs/conv remaining high after the conversion, automatic nap modes provides power reduction at reduced sample rate.
ltc1863/ltc1867 14 18637f applicatio s i for atio wu u u figure 7. example 2, cs/conv starts a conversion with short active high pulse. with cs/conv returning low before the conversion, the adc remains powered up. input voltage (v) output code 1867 f09 111...111 111...110 100...001 100...000 000...000 000...001 011...110 011...111 fs ?1lsb 0v unipolar zero fs = 4.096 1lsb = fs/2 n 1lsb = (ltc1863) = 1mv 1lsb = (ltc1867) = 62.5 v figure 8. ltc1863/ltc1867 bipolar transfer characteristics (twos complement) figure 9. ltc1863/ltc1867 unipolar transfer characteristics (straight binary) s0 sd 0s s1 com uni slp msb = d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cs/conv sck sdi sdo (ltc1867) hi-z 12345678910111213141516 t conv d12 msb = d15 d14 d13 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hi-z 1867 f07 t conv don't care don't care not needed for ltc1863 t acq sdo (ltc1863) input voltage (v) 0v output code (two? compliment) ? lsb 1867 f08 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 ?1lsb fs/2 fs = 4.096 1lsb = fs/2 n 1lsb = (ltc1863) = 1mv 1lsb = (ltc1867) = 62.5 v
ltc1863/ltc1867 15 18637f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc1863/ltc1867 16 18637f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2004 lt/tp 0504 1k ? printed in usa related parts part number description comments ltc1417 14-bit, 400ksps serial adc 20mw, unipolar or bipolar, internal reference, ssop-16 package lt1460 micropower precision series reference bandgap, 130 m a supply current, 10ppm/ c, sot-23 package lt1468/lt1469 single/dual 90mhz, 22v/ m s, 16-bit accurate op amps low input offset: 75 m v/125 m v ltc1609 16-bit, 200ksps serial adc 65mw, configurable bipolar and unipolar input ranges, 5v supply lt1790 micropower low dropout reference 60 m a supply current, 10ppm/ c, sot-23 package ltc1850/ltc1851 10-bit/12-bit, 8-channel, 1.25msps adc parallel output, programmable mux and sequencer, 5v supply ltc1852/ltc1853 10-bit/12-bit, 8-channel, 400ksps adc parallel output, programmable mux and sequencer, 3v or 5v supply ltc1860/ltc1861 12-bit, 1-/2-channel 250ksps adc in msop 850 m a at 250ksps, 2 m a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 3v, 12-bit, 1-/2-channel 150ksps adc 450 m a at 150ksps, 10 m a at 1ksps, so-8 and msop packages ltc1864/ltc1865 16-bit, 1-/2-channel 250ksps adc in msop 850 m a at 250ksps, 2 m a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 3v, 16-bit, 1-/2-channel 150ksps adc in msop 450 m a at 150ksps, 10 m a at 1ksps, so-8 and msop packages

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